The invention relates to delay-lock loops (DLLs). More particularly, the invention relates to a DLL circuit and method for an integrated circuit (IC).
Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the flip-flops in a circuit may change state. Clearly, clocks are often heavily loaded signals, and may be bussed throughout a very large IC. Even with specially-designed global buffers, there is typically a delay between the clock edge received by the IC at the pad, and the clock edge received by the last-served flip-flop on the IC (i.e., between the xe2x80x9cinput clock signalxe2x80x9d and the xe2x80x9cdestination clock signalxe2x80x9d). This delay, designated herein as td, may cause difficulties in interfacing between ICs, or simply slow down the overall system speed. Input data may be provided in synchronization with the input clock signal, while output data is typically provided in synchronization with the destination clock signal. Further, td often varies not only between different ICs, but on a single IC with temperature and voltage as well. It is highly desirable to have a circuit and method for synchronizing a destination clock signal with an input clock signal, so that the destination clock signals of various ICs can be commonly synchronized by synchronizing each destination clock signal to a common input clock signal.
This clock synchronization procedure is often performed using a phase-lock loop (PLL) or delay-lock loop (DLL). However, known PLLs and DLLs consume a great deal of silicon area. Additionally, PLLs are often analog in nature and take an extremely long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Further, analog PLLs can be particularly sensitive to radiation. Therefore, PLLs are very difficult to design, and often are not feasible in a given circuit or system.
Known DLLs are also very complicated and difficult to design. Further, known DLLs require many input clock cycles to xe2x80x9clockxe2x80x9d, i.e., to synchronize a destination clock signal to an input clock signal. As described below, known DLLs also typically run continuously during the entire time the two clock signals must be synchronized, frequently adjusting the destination clock signal to keep it properly synchronized. This constant adjustment not only requires a large and complicated state machine, it also injects a lot of noise into the clock network. Because a noisy clock signal can cause enormous problems in a sensitive IC circuit, a large stabilizing capacitor is often required between the positive power supply (VDD) and the zero voltage level (ground). For one or more of these reasons, clock synchronization is often not feasible using known circuits and methods.
Therefore, it is desirable to provide a delay-lock loop circuit and method using a fairly simple circuit that consumes a relatively small amount of silicon area and locks in a few clock cycles.
Additionally, it is desirable to provide a phased output clock signal, i.e., a series of output clock signals that become active sequentially in a repeating sequence. For example, when four phased output clock signals are provided, each output clock signal can be used to clock only one-fourth of a large circuit at any given time, thus reducing the maximum current flow in the circuit. Phased clocks are also easier to use in circuits that require pre-charge and evaluation clock phases.
The invention provides a delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. A single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. Further, only one delay line is required to implement the DLL circuit. Therefore, the DLL of the present invention is both quick to xe2x80x9clock inxe2x80x9d a clock signal and efficient in the use of hardware resources. Further, the present DLL is very accurate, because the same delay line is used to calculate the necessary additional delay and to generate the output clock signal.
A circuit according to the invention includes an input clock terminal supplying an input clock signal, a feedback clock terminal supplying a feedback clock signal, a delay line, and a control circuit controlling access from the input clock terminal and the feedback clock terminal to the delay line. The DLL has two modes. In the first (or xe2x80x9ccountingxe2x80x9d) mode, the delay line supplies to a decoder circuit a first plurality of intermediate clock signals delayed from the feedback clock signal by incremental unit delays. In the second (xe2x80x9cor operatingxe2x80x9d) mode, the value provided to the decoder circuit in the first mode is latched, while the delay line supplies to a clock multiplexer a second plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays.
The clock multiplexer uses the latched decoder circuit value to select from among the second intermediate clock signals the clock signal that provides the necessary additional delay to.synchronize the feedback clock signal to the input clock signal, i.e., the clock signal subject to a delay about equal to (e.g., closest to but not exceeding) the delay needed to bring a first (e.g., rising) edge of the feedback clock signal into synchronization with the same (e.g., rising) edge of the input clock signal. The output clock signal from the clock multiplexer is distributed through the clock network to provide the distributed clock signal as well as the feedback clock signal. (In another embodiment, the intermediate clock signal selected by the clock multiplexer is the intermediate clock signal subject to a delay closest to and exceeding the delay needed to synchronize the feedback and input clock signals.)
The decoder circuit essentially counts the number of unit delays between a first (e.g., rising) edge of the feedback clock signal and the same (e.g., rising) edge of the input clock signal. This delay period is the additional delay that must be added by the DLL to bring the two clocks into synchronization. This number is then used to select the correct intermediate clock signal.
An advantage of the invention is that once the two clocks are synchronized, they need not be resynchronized unless the frequency of the input clock signal changes. Although the feedback clock signal may not be exactly synchronized to the input clock signal (the degree of accuracy depending on the granularity of the unit delay compared to the measured delay), the offset between the two clock signals does not change with time, and no subsequent adjustments need be made, as with prior art DLL circuits. Therefore, the circuit and method of the invention inject significantly less noise into the IC than known methods. Further, this xe2x80x9cone-shotxe2x80x9d capability (i.e., the ability to synchronize the two clocks in a single synchronization step) means that the circuit of the invention is much easier to simulate, and thus to design, than known DLL circuits.
Another advantage of the invention is that the circuit is smaller and therefore less expensive to implement than known DLL circuits, because no large state machine is required. Therefore, using the DLL circuit of the invention, clock synchronization capability can be added to smaller and less expensive ICs than was previously feasible. Further, only one delay line is required to implement the circuit, thereby both.reducing the size of the circuit and ensuring exact matching of unit delays between the xe2x80x9ccountingxe2x80x9d phase (the first mode) and the xe2x80x9coperatingxe2x80x9d phase (the second mode).
Other embodiments of the invention provide phased output clock signals. In these embodiments, in the xe2x80x9ccountingxe2x80x9d mode, in addition to counting the number of unit delays necessary to synchronize the clocks, the circuit also counts the number of incremental unit delays between a first (e.g., rising) edge of the feedback clock signal and the next same (e.g., rising) edge of the feedback clock signal. The resulting number is the number of incremental unit delays in a single feedback clock period, which is also the number of incremental unit delays in a single input clock period. This number is divided by a number of desired output clock phases (e.g., four), and the result is used to generate the phased clock signals.
One such embodiment includes a latch circuit, a second decoder circuit, and a phase generator circuit. The delay line supplies to the latch circuit the first plurality of intermediate clock signals delayed from the feedback clock signal by incremental unit delays. The latch circuit counts and stores a value representing the number of incremental unit delays in a single feedback clock period. The second decoder circuit decodes the stored value and provides to the phase generator circuit a plurality of phase select signals that control the number of unit delays between each phased output clock.